1. Field of the Invention
Embodiments of the present invention relate to a memory device or a method of controlling input signals input into a memory device. In embodiments, separation of data and addresses from input signals is controlled. This application claims the priority of Korean Patent Application No. 2003-76215, filed on Oct. 30, 2003, in the Korean Intellectual Property Office, the disclosure of which is incorporated herein in its entirety.
2. Description of the Related Art
Through the development of input/output (I/O) interface technology, a variety of I/O interface technologies have been adopted in memory devices. Such I/O interface technologies include differential signaling technology. In differential signaling technology, a pair of input signals having opposite phases are input into a memory device.
Compared to single-ended signaling technology (where a reference signal and an input signal are applied to a memory device), differential signaling technology can improve signal margin and decrease noise. However, differential signaling technology requires twice as many I/O pins compared to single-ended signaling technology. Even if a memory device usually has a high operating frequency, memory cells and cores are tested using a tester at a low operating frequency in a test mode. Further, in each stage of a test (e.g. a wafer test, a monitor burn-in test (MBT), and a package test), a method of inputting data and addresses to test memory cells and cores are different. In other words, while both the data and the address may be input through one input pin in the wafer test stage, the data and the address may be input through separate input pins in the MBT stage or the package stage.
Due to the limited number of pins and a complex design, memory devices that use single-ended signaling technology may be limited to either a first test mode (in which data and addresses are input through one pin) or a second test mode (in which data and addresses are inputted separately).